Category:Anatomy books1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a circuit for controlling a refresh operation in a dynamic random access memory (DRAM).
2. Description of the Related Art
Generally, a DRAM cell consists of one transistor and one capacitor, wherein the data stored in a DRAM cell is stored in the capacitor. Due to a finite amount of time for a charge to be stored in the capacitor, the data stored in a DRAM cell is vulnerable to loss of the data as time passes. Thus, the DRAM must have a refresh circuit for preventing the loss of the data.
A refresh operation is performed whenever the data stored in a DRAM cell is altered, so as to prevent loss of the data, and is performed periodically. More specifically, a refresh operation is periodically performed whenever a row address and a column address of a DRAM are altered.
FIG. 1 is a block diagram of a DRAM according to the related art. As shown, a DRAM consists of an address buffer 10, a row address decoder 12, a word line driver 14, a cell data buffer 16, a column address decoder 18, a sense amplifier 20, a pre-charge/equalize circuit 22, a column decoder 24, a row decoder 26, a refresh counter 28, a refresh controller 30, and a timing generator 32.
During a refresh operation, the timing generator 32 generates a column access timing signal CSPT, a row access timing signal RPT, and a write timing signal WP. The row decoder 26 receives an active row address and decodes the active row address to select a word line (not shown) in the DRAM.
The cell data buffer 16 receives the output of the row decoder 26 and the input of the column decoder 24. The column decoder 24 decodes an input column address and generates a column selection signal COL to select a column.
The refresh counter 28 receives a refresh signal REF from the refresh controller 30 and generates a refresh address signal REFA, thereby controlling a refresh operation.
The row access timing signal RPT generated from the timing generator 32, when input to the word line driver 14, activates the word line (not shown) in response to the input row address. When the word line is activated, data stored in a cell connected to the activated word line is transmitted to the cell data buffer 16.
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